The present invention relates to a unit gain output stage employing a pair of field effect transistors (FET), as output power devices, driven in class AB mode, particularly suited for monolithically integrated power amplifiers.
The designations of Class A, Class B, Class AB, and Class C amplifiers refer to ways of amplifying a bipolar signal, and specifically how an amplifier handles zero-crossings. One extreme case is Class A, where the driver devices of the output stage pass a DC current component which is so large that no zero-crossings occur at all. Another extreme case is Class C, where the output is "center-clipped," i.e. the output signal cuts off when the magnitude of input signal is within a certain band around zero. Both of these have great disadvantages: Class A is extremely wasteful of power, and Class C introduces a very large amount of distortion. Class B is an idealized intermediate case, where the output signal passes through zero at the same time as the input signal (unlike Class A), but no center clipping occurs (unlike Class C). (That is, in Class B one output driver drives the output positive when the input is positive, and the other output driver drives the output negative when the input is negative.) However, in practice it is very difficult to operate precisely in Class B, since the turn-off and turn-on of the two output drivers must be precisely matched to avoid crossover distortion (around the zero-crossing); so for audio and precision applications a Class AB mode is often used. This mode is basically a modification of Class B in which both output drivers are passing a small amount of current at the moment when the input signal crosses through zero. This avoids distortion without greatly increasing power consumption.
A technical problem of class AB power amplifiers employing FETs, for example a pair of n-channel MOS transistors, relates essentially to the ability of effectively controlling the quiescent current flowing through the pair of output power transistors and of reducing the so-called crossover distortion.
The necessity of controlling the quiescent current derives from the inevitable compromise between the desirability of reducing power dissipation, which requires a low quiescent current Iq, and of minimizing crossover distortion caused by the non-linearity of the operating characteristics of the output devices, which non-linearity may become intolerably pronounced at relatively low bias current levels.
Thus for maximum linearity, it is desirable to keep the minimum gate voltage close to the threshold voltage. However, if the minimum gate voltage is above the threshold voltage, a significant quiescent current will flow, since neither power transistor will ever turn off completely. This causes excess power consumption, and excess heat dissipation in the power devices, both of which are undesirable.
Another well known cause of crossover distortion resides in the fact that, in a simple switching circuit, one or the other of the two output power transistors alternatively turn-off completely during a complete cycle, and distortion is caused by the consequent turn-on delays that occur. Obviously the problem of crossover distortion becomes more marked at high frequency.
In the relevant literature, there are many examples of circuits for controlling the bias (quiescent) current. Two particularly interesting articles are B. Roehr, "A simple direct-coupled power MOSFET audio amplifier topology featuring bias stabilization", by IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 546 (1982), and the article entitled "Une autre conception de l'amplificateur de puissance", published as application note AN80-5 at pages 75-79 of the Siliconix catalog distributed in France.
The Roehr article describes a power amplifier wherein the biasing current of the output power devices is controlled by means of a complex system that detects the quiescent current Iq, and which is based on a limiting circuit, followed by a filter. The stabilization circuit employs, among other devices, an operational amplifier and a large capacitor. Significantly, the capacitor used has a capacitance that is two orders of magnitude higher than the capacitance of the other capacitors employed in the circuit, as shown at page 550.
The amplifier circuit described in the Siliconix application note is similar to that in the Roehr article, but without the circuit for detecting quiescent current Iq. In this circuit, the control of the quiescent current Iq is implemented by a potentiometer, as shown in the circuit diagram at page 78.
The above known solutions for implementing a control of the output stage, and particularly the fact that they require the use of either a large capacitor or a potentiometer, makes them unsuitable to be realized in a fully integrated form.
Moreover, as depicted at page 79 of the Siliconix application note, the driving circuit of the two output power transistors employs PNP bipolar transistors having a relatively high current carrying capacity. Should a monolithic integration of the driving circuit be considered, the presence of PNP transistors will require a relatively large area of integration. It is generally convenient to limit the number of PNP transistors to a minimum.
A step forward in improving these techniques is represented by the output stage disclosed in U.S. Pat. No. 5,216,381 of SGS-Thomson Microelectronics S.R.L. (issued from patent application Ser. No. 07/808,489). In that application a unit gain output stage employing a pair of power FETs, particularly suited for integrated power amplifiers, and which effectively reduces crossover distortion, irrespectively of its origin, is disclosed. Moreover, the circuit does not require the use of practically non-integratable components, such as large capacitors, potentiometers and the like, notwithstanding the fact that the circuit is perfectly capable of effectively controlling the quiescent current through the field effect output power transistors. The pertinent description contained in the above-noted U.S. patent application is herein incorporated by express reference.
In many applications, a limitation of power dissipation within the chip containing the functional circuits of the drive amplifier is required. Often, this is obtained by realizing one or both of the output power transistors, driven in class AB, in discrete form or in any case outside the integrated circuit containing the drive amplifier. A typical example or situation of this type is that of an integrated circuit containing the drive amplifier of a so-called external Voice Coil Motor (VCM), that can be driven in class AB mode.
A general objective of device manufacturers is that of realizing the entire drive circuit in a single chip, mounted in a single package, with characteristics of substantially "universal" utility. In other words, the same IC should advantageously be usable by a manufacturer of apparatuses in a large number of applications that may contemplate different levels of the excitation current delivered to a VCM motor or the like, and therefore different values of power dissipation by simply choosing the value of external components depending upon the specific requisites of the application. The advantages that would be derived are manyfold, both in terms of a reduced cost of the package (which may be a standard low cost type, without heat sink if the output power transistors are external) and of the possibility of producing the integrated circuit for relatively large sale volumes.
On the other hand, when the output power transistors are outside the device containing the integrated drive circuit and the handled power is no longer dissipated within the integrated circuit, the circuit must be capable of driving the two external power devices, while controlling their operating condition under any situation of operation, independent of their intrinsic characteristics. In fact, with the power devices external to the integrated circuit, it is necessary, according to a well known technique, to sense the current actually delivered to the load (commonly done with sensing resistances). The need to employ external sensing resistances of the current is in contrast with a general requirement of reducing to the minimum the number of external components.
Also in the power amplifier circuit described in the cited prior U.S. Pat. No. 5,216,381, advantageously employing a pair of field effect transistors (FETs) as output power elements should be required to realize the two output power transistors outside an integrated driving circuit, external sensing resistances of the current will be necessary in order to implement an effective control of the operating conditions of the two power FETs.
The present application provides an innovative and effective method and device for controlling the operation of a pair of power transistors, at least one of which is externally connected to the integrated circuit containing the driving and controlling circuitry of the two output power transistors, which advantageously does not require any external sensor of the operating condition of an externally connected power transistor or of said pair of external transistors.
An important innovative teaching of the present application is using a buffer stage for driving one of a pair of output power transistors that is connected externally to the integrated circuit and which, in case of a pair of n-channel output power transistors, will be the pull-up or upper transistor, while in the case of a pair of p-channel output transistors, will be the pull-down or lower transistor of the pair. The buffer stage may be functionally connected between the output node of an amplifying stage of the driving signal and a control terminal (gate) of the driven external transistor of the output pair. The invention further employs a limiting network comprising at least a field effect transistor, which may be directly driven by the output node of the signal amplifying stage and a resistance functionally connected in series with the transistor. The so-constituted limiting network is connected between a supply node (VCC) and the output node of the output power stage.
In practice, the limiting network virtually reproduces within the integrated control circuit either a pull-up ("high side") transistor (in the case of an n-channel output transistor pair), or a pull-down ("low side") transistor (in the case of a p-channel output transistor pair), provided with a resistance in series with its drain terminal, while the buffer that drives the "homologous" external power transistor has the function of shifting, respectively toward ground potential or toward the supply voltage, the level of the input signal by a value equal to the threshold voltage of the field effect transistor of the limiting network, under quiescent bias conditions. In this way, under quiescent conditions, the voltage between the gate and the source of the external output power transistor is null thus ensuring the turning-off of the external power transistor, independently of the value of its intrinsic threshold voltage.
When the current absorbed by the load increases, the voltage V(OP1), present on the output node of an operational amplifier OP1 that amplifies the driving signal increases, thus bringing the field effect transistor of the limiting network toward saturation. On the other hand, since the maximum current that flows through the transistor of the limiting network is limited by the resistance in series with its drain, when the current drawn by the load becomes larger than such a maximum current that may be delivered by the transistor of the limiting network, the voltage V(OP1) on the output node of the signal amplifier OP1, will increase further and so the output voltage of a buffer BF1 that drives the external power transistor will also increase, until it reaches a voltage such as to satisfy the following relationship: EQU V(OP1)&gt;Vthexternal+V(output)
thus turning-on the external power transistor.
In this way, the burden of delivering the current difference between the current required by the load and the maximum current that can be delivered by the integrated transistor of the limiting network is transferred to the external power transistor.
Unlike the known solutions, the circuit of the invention does not require the use of any external components for detecting the load current and advantageously may employ field effect transistors, for example DMOS transistors, capable of greatly reducing power dissipation as compared with bipolar power transistors of similar current-handling capability.
By virtue of the fact that the operation of the circuit is substantially independent of the threshold voltage of the other power transistor of the output pair (n-channel or p-channel), the fact that also such other transistor of the output pair be realized within the integrated driving circuit or not becomes substantially insignificant.
Therefore, depending on the contemplated application, one only or both the output power transistors may be external to the integrated circuit containing the driving and control circuitry.